Forbes

SiFive Is Leading The Way For Innovation On RISC-V

The company appears well positioned to challenge CPU incumbents with high performance RISC-V CPUs and Vector Extensions to the open ISA architecture. The RISC-V CPU Instruction Set Architecture (ISA) ...
Business Wire

SiFive To Introduce New RISC-V Processor Architecture and RISC-V PC at Linley Fall Virtual Processor Conference

SAN MATEO, Calif.--(BUSINESS WIRE)--SiFive, Inc., the leading provider of commercial RISC-V processor IP and silicon solutions, today announced that Dr. Yunsup Lee, CTO of SiFive, and Dr. Krste ...
Geeky Gadgets

RISC-V Vector Processing: A New Era in Computing Efficiency

The computing industry has reached a significant milestone with the ratification of the 1.0 RISC-V Vector Specification. This development marks the beginning of a new era in computing efficiency, as ...
EDN

Ceva develops DSP architecture for 5G Advanced

Ceva, Inc. has unveiled its fifth generation CEVA-XC DSP architecture, the CEVA-XC20, at Mobile World Congress (MWC) 2023. The CEVA-XC20 is based on a new vector multi-threaded massive compute ...
Network World

Cray to unite scalar, vector computer architectures

Cray plans to create a new supercomputing platform combining four types of processing capability in a blade server architecture. Cray Inc. plans to create a new supercomputing platform combining four ...
Semiconductor Engineering

Multi-Core Architecture Optimized For Time-Predictable Neural Network Inference (FZI, KIT)

A new technical paper titled “MultiVic: A Time-Predictable RISC-V Multi-Core Processor Optimized for Neural Network Inference” was published by researchers at FZI Research Center for Information ...