Agilent Technologies has announced a strategic partnership with Aster Technologies to enable integration of Aster's TestWay Coverage Analyst with Agilent's printed-circuit-board assembly-test ...

February 5, 2013. ASTER Technologies, a supplier of board-level testability and test-coverage analysis products, has developed a new release of TestWay in support of “Design for Excellence” (DfX) ...

The growth in safety-critical applications has ushered in a paradigm shift in automotive IC functional safety and test coverage analysis. The increased need for safety, low defect rate, and long-term ...

Scan is a structured test approach in which the overall function of an integrated circuit (IC) is broken into smaller structures and tested individually. Every state element (D flip-flop or latch) is ...

For years the process of ASIC and FPGA design and verification debug consisted primarily of comprehending the structure and source code of the design with waveforms showing activity over time, based ...