Design-Reuse

Springer Publishes ARM-Synopsys Verification Methodology Manual for SystemVerilog

New ARM-Synopsys Book Provides Blueprint for System-on-Chip Verification Success Using SystemVerilog NEW YORK -- Sept. 21, 2005 -- Springer Science + Business Media, Inc., a major publisher of ...
EDN

SystemVerilog assertions unify design and verification

The SystemVerilog standard is the result of an industry-wide effort to extend the Verilog language in a consistent way to include enhanced modeling and verification features. By adding verification ...
EDN

Using SystemVerilog for functional verification

The need to improve functional verification productivity and quality continues to grow. The 2004/2002 IC/ASIC Functional Verification Study, by Collett International Research, shows that logic or ...
Design-Reuse

Development of Verification Environment for Layered Protocol using SystemVerilog

Today, functional verification consumes most of the time in the design of layered protocols like OSI Model, PCI Express, etc. As we think of reuse of design components, the reuse of verification ...
Electronic Design

SystemVerilog Gains A Foothold In Verification

SystemVerilog marries a number of verification concepts, primarily in the areas of design, assertions, and testbench creation, that were previously embodied in separate and sometimes proprietary ...