EDN

Commentary: SystemVerilog enables design with verification

The SystemVerilog language standard is one of the hottest topics in EDA today, and with good reason. It takes a huge step up from traditional hardware description languages, incorporating key concepts ...
EDN

Moving from Vera to SystemVerilog 3.1

Over the past decade, Hardware Verification Languages (HVL) such as Vera have become popular for implementing verification plans. Numerous companies have successfully adopted Vera in their ...
Design-Reuse

'Smart' verification moves beyond SystemVerilog 3.0

Functional verification is consuming an inordinate amount of the design cycle. Estimates vary, but most analysts and engineers agree that as much as 70 percent of the design cycle is consumed by ...
Semiconductor Engineering

Simplifying SystemVerilog Functional Coverage

Let’s say you have a block you need to verify. How do you know that the stimulus you are about to use is exhaustive enough and that you have covered the necessary scenarios/situations to prove it is ...
Business Wire

Benefit from the Power of the Latest SystemVerilog Subset Constructs – with Confidence

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., an industry leader in Electronic Design Verification, has expanded the rule-checking capabilities of its popular ALINT-PRO™ tool in response to the ...
Electronic Design

First Commercial Parser Ships For System Verilog

A sure sign that a design language is making its way into the mainstream is the appearance of a spate of tools supporting it. For SystemVerilog devotees, the latest good news is the commercial ...
Ars Technica

Breaking into ASIC Design/Verification

I'm fast approaching the one year mark with my current employer since I graduated last year. Previously, I did three four month work terms with them and they were for the most part interesting. I took ...
Business Wire

Verific Ships First Commercially Available SystemVerilog Parser

Verific Design Automation, the leading provider of Verilog and VHDL front ends for electronic design automation (EDA) applications, today announced that it is shipping the first commercially available ...
Design-Reuse

TransEDA adds SystemVerilog support and Advanced Rule checking to its leading Verification Navigator tool suite

Eastleigh UK - Paris France, January 24, 2005 – TransEDA, the leader in coverage and ready-to-use verification solutions for electronic designs, today announces SystemVerilog support in new versions ...
Yahoo Finance

Accellera Approves Verilog-AMS 2023 Standard for Release

ELK GROVE, Calif., March 04, 2024 (GLOBE NEWSWIRE) -- Accellera Systems Initiative (Accellera), the electronics industry organization focused on the creation and adoption of electronic design ...