SAN FRANCISCO — Summit Design Inc. has introduced an integrated development environment (IDE) for SystemC-based analysis and debug. The tool, Vista 1.1, is an improved version of the Vista IDE that ...
Sometimes design abstraction is a help, and sometimes it's a hindrance. Verification of system-on-a-chip designs with SystemC has a demonstrated ability to significantly speed up simulation runs.
Henderson, Nevada - December 27, 2004-- Aldec, Inc., a pioneer in mixed-language simulation and advanced design tools for ASIC and FPGA devices, today announced the release of Riviera 2004.12. The new ...
SANTA CRUZ, Calif. — Expanding its capabilities for mixed-language simulation of ASICs and FPGAs, Aldec Corp. this week (Dec. 27) announced the release of Riviera 2004.12. New features include ...
Los Altos, CA – June 2, 2005 – Summit Design, Inc., a leading provider of electronic system-level (ESL) design solutions, today announced the release of Vista™ 1.1, an integrated development ...
STATE takes a SystemC design as input and transforms it into a corresponding UPPAAL timed automata model. The transformation is based on a formal semantics defined for SystemC in ...
An increasing number of embedded designs are multi-core systems. At the pre-silicon stage, customers use a simulation platform for architectural exploration and software development. Architects want ...
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