Tessera Technologies Inc. has unveiled a tiny stacking package that enables users to mix and match independently tested silicon devices and stack them within a single-chip footprint. The company's ...

An advanced packaging technology has been developed that allows the mechanical stacking of chip-scale memory devices using a fine-pitch ball grid array (FBGA) interface. Significantly reducing ...

Broadcom has introduced its 3.5D eXtreme Dimension System in Package (3.5D XDSiP) platform for ultra-high-performance processors for AI and HPC workloads. The new platform relies on TSMC's CoWoS and ...

A multi-domain passive module with functionality embedded in the substrate has been developed by Saras Micro Devices. The Saras Tile, or STILE, enables power regulation from system board to package.

Manufacturing-aware system design treats dies, interposers, packages, and analysis as a single, coherent system.

Demands for lower-cost, higher-density, and smaller-footprint ICs aimed at portable electronics make 3D-packaging designers sweat. The push for 3D packaging of semiconductor ICs directly results from ...

YOKOHAMA, Japan, Aug. 27, 2025 /PRNewswire/ -- Socionext, the Solution SoC company, today announced the availability of 3DIC support in its portfolio of well-proven capabilities for the delivery of ...