Semiconductor Engineering

Interface DRC Can Streamline Chip-Level Interface Physical Verification

In most design companies, the chip-level physical implementation teams responsible for design floorplanning in place and route (P&R) environments also manage top-level physical verification from the ...
EDN

Physical Design Flow Taps Partition Layout

Detailed and precise hierarchical design planning is essential to achieving closure on large designs. In this article we describe a new hierarchical design flow and its usage on a 3 million-gate chip.
EDN

Physical design and architectural design

Historically, in the semiconductor-design flow, tapeout came after the last stages of the physical-design creation and verification. It was the final step before the design entered the manufacturing ...
Design-Reuse

Beyond DDR2 400: Physical Implementation Challenges in Your SoC Design

High performance DDR2 SDRAM is an increasingly common memory solution for designs requiring improved data bandwidth capabilities, lower power, and enhanced signaling features. However, the benefits of ...
Design-Reuse

eInfochips Launches Physical Design Services - Addresses Entire Chip Design Cycle

SANTA CLARA, Calif., April 6-- eInfochips announced that it will provide physical design services together with its existing portfolio of front-end design & verification services. The company's ...