Morning Overview on MSN

Lattice Semiconductor wins a gold cybersecurity award for the first FPGA with post-quantum cryptography baked in

Lattice Semiconductor picked up a gold cybersecurity award in May 2026 for what the company says is the industry’s first ...
Morning Overview on MSN

Lattice delivers first FPGA family with CNSA 2.0 post-quantum cryptography — wins gold for best security solution

Lattice Semiconductor has begun shipping what it says is the first FPGA family built to meet the NSA’s CNSA 2.0 post-quantum ...
EDN

Tool develops FPGA algorithms from C/C++

CoDeveloper FPGA design tool allows algorithms to be developed and debugged with existing C/C++ tools. The tool helps identify dataflow bottlenecks, generates debugging visualizations for ...
EDN

Targeting Floating-Point Algorithms for FPGA or ASIC Deployment

Native Floating-Point HDL code generation allows you to generate VHDL or Verilog for floating-point implementation in hardware without the effort of fixed-point conversion. Native Floating-Point HDL ...
Design-Reuse

Altera FPGAs Achieve Compelling Performance-per-Watt in Cloud Data Center Acceleration Using CNN Algorithms

San Jose, Calif., —February 23, 2015—Altera Corporation (NASDAQ: ALTR) today announced Microsoft (NASDAQ: MSFT) is using Altera Arria® 10 FPGAs (field programmable gate arrays), to achieve compelling ...
Electronics Weekly

How to move design algorithms to the FPGA

There are many types of designs being put into FPGAs today, but one type of design stands out – image and signal processing algorithms – because of its significant role in providing product ...
Yahoo Finance

MicroCloud Hologram Inc. FPGA-Based High-Performance Surface Code Quantum Simulation Platform: Efficient Error Correction Algorithm Validation under Rotated Layout

SHENZHEN, China, Feb. 25, 2026 /PRNewswire/ -- MicroCloud Hologram Inc. (NASDAQ: HOLO), ("HOLO" or the "Company"), a technology service provider, has developed a surface code quantum simulator based ...
Design-Reuse

FPGA algorithm tunes gray, color images

For both gray-scale and color image applications in an FPGA, we have implemented block truncation coding (BTC), a lossy image-compression algorithm with proven value in applications that don't require ...
Electronics Weekly

VMetro FusionXF FPGA development kit for embedded DSP systems

VMetro’s FusionXF FPGA development kit is targeted at reducing the design time and optimizing the performance of complex FPGA and PowerPC processing systems. It aids in the development of their FPGA ...
New Electronics

Microchip releases C++ synthesis suite for PolarFire FPGA algorithm development

Microchip Technology has added an HLS design workflow, called SmartHLS, to its PolarFire FPGA families to allow C++ algorithms to be directly translated to FPGA-optimised Register Transfer Level (RTL) ...