EDN

Implementing custom DDR and DDR2 SDRAM external memory interfaces in FPGAs (part 2)

Note: This is the second part of a two-part article covers the remaining steps to implement DDR or DDR2 external memory interfaces (EMIFs) using FPGAs via ALTDLL and ALTDQ_DQS megafunctions. Steps 4 ” ...
Business Wire

Intel Announces Unmatched AI and Analytics Platform with New Processor, Memory, Storage and FPGA Solutions

SANTA CLARA, Calif.--(BUSINESS WIRE)--What’s New: Intel today introduced its 3rd Gen Intel® Xeon® Scalable processors and additions to its hardware and software AI portfolio, enabling customers to ...
The Next Platform

A Cornucopia Of Memory And Bandwidth In The Agilex-M FPGA

March 8, 2022 Timothy Prickett Morgan Compute Comments Off on A Cornucopia Of Memory And Bandwidth In The Agilex-M FPGA When it comes to memory for compute engines, FPGAs – or rather what we have ...
Design-Reuse

Dual-port FPGA memory blocks: the ultimate system interconnect solution?

The performance of dual-ports memory blocks in FPGAs is highly dependent on device utilization and how these blocks are instantiated. Using dual-port memories ("dual ports") as system interconnects ...
Nasdaq

Altera Starts Production Shipments of Industry’s Highest Memory Bandwidth FPGA

Agilex 7 FPGA M-Series Optimized to Reduce Memory Bottlenecks in AI and Data-intensive Applications SAN JOSE, Calif.--(BUSINESS WIRE)-- Altera Corporation, a leader in FPGA innovations, today ...
Hackaday

NEO430 Puts A Custom MSP430 Core In Your FPGA

We are certainly spoiled by all the microcontroller options nowadays — which is a great problem to have. But between the good old 8-bit controllers and an increasing number of 32-bit varieties, it ...
The Next Platform

FPGA Based Deep Learning Accelerators Take on ASICs

Over the last couple of years, the idea that the most efficient and high performance way to accelerate deep learning training and inference is with a custom ASIC—something designed to fit the specific ...
Design-Reuse

Lattice Semiconductor Launches LatticeSC System Chip FPGA Family

LatticeSC FPGA Combines High-Speed I/O, SERDES, Structured ASIC Blocks and High Performance FPGA Fabric On a Single Device HILLSBORO, OR – FEBRUARY 8, 2006 – Lattice Semiconductor Corporation ...
Electronic Design

M.2 Module Merges FPGA and 32-GB Memory

The PCI Express (PCIe) interface supports NVMe, which is de facto high-speed storage interface. The module supports computational storage processor (CSP) configurations—CSPs are becoming more popular ...
EDN

Implementing custom DDR and DDR2 SDRAM external memory interfaces in FPGAs (part 1)

These design guidelines provide the best practices for DDR and DDR2 SDRAM custom memory interface implementation in Stratix III and Stratix IV FPGAs. Figure 1 shows the design flow that is required ...
Business Wire

Altera Starts Production Shipments of Industry’s Highest Memory Bandwidth FPGA

SAN JOSE, Calif.--(BUSINESS WIRE)--Altera Corporation, a leader in FPGA innovations, today announced production shipments of its Agilex™ 7 FPGA M-Series, the industry's first high-end, high-density ...