Lack of coordination between asynchronous resets and synchronous logic clocks leads to intermittent failures on power up. In this series of articles, we discuss the requirements and challenges of ...

At 0.18 micron and below, handling crosstalk becomes a significant design challenge. Historically safe and pervasive design techniques may now increase crosstalk, and must be reviewed for suitability.

To meet low-power and high-performance requirements, system on chip (SoC) designs are equipped with several asynchronous and soft reset signals. These reset signals help to safeguard software and ...

As the complexity of system-on-chip (SoC) designs escalates, driven by the demand for more integrated functionalities and higher performance, electronic components such as processors, power management ...

Synchronous interfaces involve a single clock domain and are relatively easy to design. However, at times, it is advantageous and necessary to have an asynchronous interface between peripherals for ...

One interesting topic of discussion is whether to use synchronous or asynchronous reset in design. In synchronous reset design, we use reset signal in the D path of flop. Hence, the assertion of reset ...

Reset is one of the most important signals in a design and yet perhaps one of the least respected. What can go wrong and how to correct it. Resets are a necessary part of all synchronous designs ...